This invention relates to a semiconductor device.
In recent years, with the trend of size reduction of semiconductor elements, the size of transistors also tends to be reduced. This trend of size reduction of transistors has made the short channel effect more prominent. For example, in the case of a DRAM (Dynamic Random Access Memory), the channel length of a transistor is reduced with the size reduction of memory cells, whereby the sub-threshold current is increased and the threshold voltage (Vt) of the transistor is reduced. As a result, the performance of the transistor is deteriorated in terms of retention and write characteristics of memory cells.
In order to solve such a problem, there have been developed, for example, a recess (trench) type FET (Field Effect Transistor) in which a groove (trench) is formed in a semiconductor substrate to provide a channel having a three-dimensional structure, as well as a fin type FET in which a fin is formed between grooves to provide a channel having a three-dimensional structure. Both of these types of transistors are able to increase the effective channel length (gate length) and hence to suppress the aforementioned short channel effect. Furthermore, they are able to realize a DRAM having fine memory cells with a minimum feature size of 60 nm or less.
Another type of DRAM has also been proposed to cope with the size reduction of memory cells, in which a buried gate type transistor having a gate electrode buried in the surface layer of a semiconductor substrate is employed as a selection transistor forming a memory cell. This type of DRAM is described, for example, in Japanese Laid-Open Patent Publication Nos. 2006-339476 and 2007-081095.
In a buried gate type transistor, a gate electrode (word line), which is buried in the surface layer of a semiconductor substrate, does not protrude above the surface of the substrate. Thus, only bit lines among wirings connected to the memory cells are located in the upper layer of the semiconductor substrate. This facilitates the layout of capacitors and contact plugs forming the memory cells when they are provided on the semiconductor substrate, and alleviates the difficulty in processing thereof.
Some of related semiconductor devices (DRAMs) are configured, as shown in FIG. 23A and FIG. 23B, such that two memory cells are arranged in each single active region. FIG. 23A is a plan view showing, partially transparently, such a semiconductor device, and FIG. 23B is a cross-sectional view of the semiconductor device taken along the line A-A′ in FIG. 23A.
Describing in more detail, this semiconductor device has an element isolation region 104 which is formed by forming a element isolation trench 102 in the surface layer of a semiconductor substrate 101 and burying an element isolation insulating film 103 in the element isolation trench 102, and a plurality of active regions 105 which are isolated from each other by the element isolation region 104.
There are formed, in the surface layer of the semiconductor substrate 101, a plurality of buried gate trenches 106a, 106b so as to extend in a direction Y intersecting with the active regions 105. These buried gate trenches 106a, 106b are arranged side by side in pairs so as to divide the active regions 105.
The semiconductor device has a gate insulating film 107 covering the surfaces of the active regions 105 exposed in the buried gate trenches 106a, 106b, word line wiring layers (word lines) WL1′, WL2′ (gate electrode 108a, 108b) buried in the buried gate trenches 106a, 106b, and a cap insulating film 109 also buried in the buried gate trenches 106a, 106b on top of the word line wiring layers (word lines) WL1′, WL2′. The word line wiring layers WL1′, WL2′ are formed such that they are buried in the buried gate trenches 106a, 106b, respectively, and cross over the active region 105 via the gate insulating film 107. As a result, the two word line wiring layers WL1′, WL2′ crossing the single active region 105 function as gate electrodes 108a, 108b of transistors Tr1′, Tr2′.
The semiconductor device has a first impurity diffusion layer 110 functioning as a drain region of the transistors Tr1′, Tr2′ in the active region 105b that is located at the center of the three active regions 105a, 105b, 105c divided by the two buried gate trenches 106a, 106b. Further, the semiconductor device has second impurity diffusion layers 111a, 111b functioning as source regions of the transistors Tr1′, Tr2′ in the active regions 105a, 105c located on the opposite sides. These first and second impurity diffusion layers 110, 111a, 111b are formed by diffusing an impurity into the active regions 105a, 105b, 105c to a depth equivalent to the level of the top faces of the gate electrodes 108a, 108b. 
An interlayer insulating film 112 is formed on the semiconductor substrate 101 so as to cover the surface 101a thereof. The first impurity diffusion layer 110 is electrically connected to a bit contact plug 114 buried in a bit contact hole 113 formed in the interlayer insulating film 112. On the other hand, the second impurity diffusion layers 111a, 111b are electrically connected to capacity contact plugs 116a, 116b buried in capacity contact holes 115a, 115b formed in the interlayer insulating film 112.
The semiconductor device has a plurality of bit wiring layers 117 (bit lines BL′) located above the surface 101a of the semiconductor substrate 101 and extending in a direction X orthogonal to the word wiring layers WL1′, WL2′. Each of these bit lines BL′ is electrically connected to the bit contact plug 114 by passing through the central part (active region 105b) of the respective active region 105. Thus, the two transistors Tr1′, Tr2′ arranged in one active region 105 share one bit line BL′.
The semiconductor device has a plurality of capacitors Ca1′, Ca2′ formed on the interlayer insulating film 112. These capacitors Ca1′, Ca2′ are each formed of a lower electrode 118, a capacity insulating film and an upper electrode (both not shown). The lower electrodes 118 are electrically connected to the capacity contact plugs 116a, 116b. Thus, the two transistors Tr1′, Tr2′ arranged in the one active region 105 form DRAM memory cells MC1′, MC2′ together with the capacitors Ca1′, Ca2′.
As described above, in the related semiconductor device, two transistors Tr1′, Tr2′ are formed in one active region 105.
Specifically, one of the transistors Tr1′ is composed of the gate electrode 108a, the first impurity diffusion layer (drain region) 110, and the second impurity diffusion layer (source region) 111a. The gate electrode 108a is buried in one of the two buried gate trenches 106a, 106b dividing the active region 105, namely in the buried gate trench 106a via the gate insulating film 107. The first impurity diffusion layer (drain region) 110 is formed by diffusing an impurity into the active region 105b located at the center of the three active regions 105a, 105b, 105c divided by the two buried gate trenches 106a, 106b, to a depth equivalent to the level of the top faces of the gate electrodes 108a, 108b. The second impurity diffusion layer (source region) 111a is formed by diffusing an impurity into one of the opposite sides of the three active regions 105a, 105b, 105c, namely into the active region 105a, to a depth equivalent to the top face of the gate electrode 108a. 
In one of the transistors, or the transistor Tr1′, a channel S1′ is formed on three faces consisting of the opposite side faces and the bottom face of the buried gate trench 106a. 
Likewise, the other transistor Tr2′ is formed to have the gate electrode 108b, the first impurity diffusion layer (drain region) 110, and the second impurity diffusion layer (source region) 111b. The gate electrode 108b is buried in the buried gate trench 106b of the two buried gate trenches 106a, 106b dividing the active region 105. The first impurity diffusion layer (drain region) 110 is as described above. The second impurity diffusion layer (source region) 111b is formed by diffusing an impurity into the other one of the opposite-side active regions of the three active region 105a, 105b, 105c, namely into the active region 105c, to a depth equivalent to the level of the top face of the gate electrode 108b. 
In the other transistor Tr2′, a channel S2′ is formed on three faces consisting of the opposite side faces and the bottom face of the buried gate trench 106b. 
However, in the semiconductor device as described above, size reduction of the transistors Tr1′, Tr2′ sometimes leads to a problem that sufficient ON current cannot be ensured for the transistors Tr1′, Tr2′ and it becomes difficult to operate the DRAM normally. This is attributable to increased channel resistance of the transistors Tr1′, Tr2′.
Further, due to the reduction of the memory cell size, the distance between two memory cells MC1′, MC2′ arranged in the single active region 105 has become smaller and smaller. This sometimes causes a trouble that when the DRAM is operated, the memory state of one of the adjacent memory cells MC1′, MC2′ varies depending on the operating state of the other memory cell, resulting in occurrence of disturb error.
For example, it is assumed that data of “0” is stored in one of the two memory cells MC1′, MC2′ arranged in one active region 105, namely in the memory cell MC1′, while data of “1” is stored in the other memory cell MC2′. When ON/OFF operation is repeatedly performed on the transistor Tr1′ of the memory cell MC1′ in this state, disturb error may occur in the other memory cell MC2′ and the data stored therein may be destroyed.
The inventor of this invention has studied possible causes of occurrence of such disturb error and has obtained findings as described below.
In the first place, data of “0” is stored in the memory cell MC1′. Specifically, one of the transistors (transistor Tr1′) is turned ON while a low-level potential is applied to the bit line BL′. Thus, the low-level potential is applied to the lower electrode 118 of one of the capacitors (Ca1′). After that, the transistor Tr1′ is turned OFF, whereby data of “0” (low-level) is accumulated in the capacitor Ca1′.
Next, data of “1” is stored in the other memory cell MC2′. Specifically, the other transistor Tr2′ is turned ON while a high-level potential is applied to the bit line BL′. Thus, the high-level potential is applied to the lower electrode 118 of the other capacitor Ca2′. After that, the other transistor Tr2′ is turned OFF, whereby data of “1” (high-level data) is accumulated in the other capacitor Ca2′.
It is assumed that in this state the same operation is repeated on the memory cell MC1′ arranged in another active region 105 using the same word line WL1′ with the memory cell MC1′. In this manner, the ON/OFF operation is repeated on one of the transistors (Tr1′) whereby a high-level potential is repeatedly applied to the word line WL1′.
The inventor has found that, during this operation, electrons (e−) induced in the channel S1′ of the transistor Tr1′ are sometimes attracted to the second impurity diffusion layer 111b of the adjacent transistor Tr2′, as shown in FIG. 23B. This is because a high-level potential is applied to the lower electrode 118 of the capacitor Ca2′ where data of “1” is accumulated. The electrons (e−) which have reached the second impurity diffusion layer 111b give a negative charge to the lower electrode 118, whereby the data of “1” (high-level data) accumulated in the other capacitor Ca2′ is rewritten to data of “0” (low-level data), resulting in occurrence of disturb error. This is the cause of the disturb error that the inventor has found.
The probability of occurrence of this disturb error is increased in dependence on the number of ON/OFF operations repeated on the transistor Tr1′. In the experiments conducted by the inventor, when the repeated ON/OFF operations were performed on the transistor Tr1′, the disturb error occurred at a frequency of about once every 10,000 operations. In this case, destruction of data will occur in about ten memory cells when 100,000 operations are repeated.
Further, little occurrence of disturb error was observed when the distance between the two word wiring layers WL1′, WL2′ crossing the one active region 105 was relatively large as about 70 nm, but the occurrence of disturb error became more frequent when the distance was reduced to about 50 nm due to reduction of the memory cell size.
The two memory cells MC1′, MC2′ arranged in the single active region 105 normally must store data independently from each other. However, when the disturb error as described above occurs, normal operation of the semiconductor device (DRAM) is inhibited, resulting in deterioration of reliability thereof.